1. Field of the Invention
This invention relates to a data transfer control device using direct memory access (DMA) method for data transfer between a memory and a peripheral, and particularly relates to a data transfer control device for easy switching between execution and inhibition of data transfer.
2. Description of the Prior Art
In an information processing system using a microcomputer, a bulk of data is often transferred between peripherals and memories, processed at the central processing unit (CPU) and then transferred to other peripherals or external storage. For example, in a print control processing system, a CPU receives data from another computer, processes the received data and, each time the printer sends a transfer request, sends a data representing one character. In such procedures, if a peripheral (printer) generates an interruption to the CPU for data transfer above using an interrupt routine, overhead at the CPU increases resulting in lower data processing efficiency of the system. To avoid such drawback, direct memory access controller (DMA controller) is used as a data transfer controller exclusively used for data transfer.
For data transfer with a DMA controller (DMA transfer), various control information including the memory address for DMA transfer and the number of DMA transfers is set in the DMA controller in advance through execution of instruction by the CPU. Then, when the DMA controller detects a DMA transfer request from a peripheral, the DMA controller requests the CPU to give the right to use the bus. When the CPU detects this request, it grants the right to use buses including the address bus and data bus to the DMA controller. The DMA controller uses an empty bus to generate address information and read/write control signal for processing to transfer the data stored in the memory to the peripheral which has generated the DMA transfer request.
When the DMA controller completes data transfer for the required number of transfers by repeating such a DMA transfer operation, it notifies the CPU of the DMA transfer completion. The CPU detecting the DMA completion executes the interrupt processing and the interrupt processing program routine. In this interruption processing program routine, the CPU resets the control information at the DMA controller to prepare for the next DMA transfer execution and starts DMA transfer again. In execution of such DMA transfer, if the memory space subjected to DMA transfer is limited, the above memory is usually divided into a plurality of areas for execution of DMA transfer so that the areas are alternatively transferred.
Conventional data transfer from a memory to a peripheral using a DMA controller is briefly described below.
A DMA controller is provided with a memory address register to store the address information to be DMA transferred and a terminal counter to store the number of transfer data, and a DMA control register having a DMA authorization bit to specify authorization/inhibition of DMA transfer. The CPU sets DMA transfer starting address to the memory address register and the number of DMA transfer data to the terminal counter before the start of DMA transfer. When the DMA controller detects DMA transfer request signal from a peripheral, it obtains the right to use the bus from the CPU and executes DMA transfer between the memory and the peripheral. The memory has, in addition to a CPU program area and a data area, a DMA transfer area divided into a plurality of areas (first and second DMA transfer areas, for example).
Before the start of DMA transfer, the CPU writes the DMA transfer data to the first DMA transfer area. After the CPU writes all of the data up to the last data in the first DMA transfer area, it sets the DMA authorization bit in the DMA control register to authorize the DMA transfer to the first DMA transfer area. This causes the DMA controller to transfer the data written to the first DMA transfer area to the peripheral. While DMA transfer for the first DMA transfer area is not executed, the CPU writes DMA transfer data to the second DMA transfer area. Upon completion of DMA transfer up to the last data of the first DMA transfer area, the DMA controller immediately starts DMA transfer for the second DMA controller. While the DMA transfer for the second DMA transfer area is not executed, the CPU writes DMA transfer data to the first DMA transfer area. Thus, the first and the second DMA transfer areas are alternatively subjected to DMA transfer.
The operation of DMA transfer between the memory and a peripheral is described next. If there occurs a need for DMA transfer at a peripheral, the peripheral activates the DMA transfer request signal and provides it to the DMA controller. Activation of the DMA transfer request signal causes the DMA controller request the right to use bus to the CPU. The DMA controller obtaining the right to use the bus, outputs the DMA transfer address information of the first DMA transfer area to the address bus and at the same time activates the memory read signal and outputs the transfer data from the memory to the bus. Then, the DMA controller activates the DMA write signal for the peripheral to write the DMA transfer data.
Each time a DMA transfer is executed, the memory address register contents are updated and the value at the terminal counter decrements by "1". If the peripheral does not generate a continuous DMA transfer request, the DMA controller notifies the CPU of abortion of the right to use the bus. When recovering the right to use bus, the CPU resumes program execution. When DMA transfer as described above is repeated until completion of data transfer for the required number of transfers (when the terminal counter value becomes "0" by decrement), the DMA controller prepares for the next DMA transfer request. It also notifies the CPU of the completion of DMA transfer by activating the DMA interruption request signal.
When such an interruption request signal ,is generated, the CPU saves the Program Counter (PC) and the Program Status Word (PSW) to the stack and activates the interrupt processing program routine. This program routine processing judges whether to continuously execute the DMA transfer or not. The routine ends without further processing for continuous execution, but resets the DMA authorization bit before termination if the transfer is not continued. Upon termination of the interrupt program routine, the CPU restores the PC and PSW from the stack.
In conventional data transfer control using DMA, as described above, the interrupt processing routine generated upon termination of DMA transfer for one DMA transfer area resets the DMA authorization bit when the next DMA transfer is not continuously executed. In this method, however, there was a drawback that DMA transfer for the next area is executed if a next DMA transfer request is generated before resetting of the DMA authorization bit.
In addition, in a conventional DMA transfer control device has another drawback that when it is required to stop DMA transfer in emergency due to an error occurring during data processing, for example, the transfer could not be stopped until DMA transfer for all the data in the area under execution is completed.